Title :
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs
Author :
Takeda, Koichi ; Saito, Toshio ; Asayama, Shinobu ; Aimoto, Yoshiharu ; Kobatake, Hiroyuki ; Ito, Shinya ; Takahashi, Toshifumi ; Nomura, Masahiro ; Takeuchi, Kiyoshi ; Hayashi, Yoshihiro
Author_Institution :
LSI Res. Lab., Renesas Electron. Corp., Kawasaki, Japan
fDate :
4/1/2011 12:00:00 AM
Abstract :
A multi-step word-line control technology (MWC), combined with a new hierarchical cell SRAM architecture (HCA), has been developed to overcome rapid increase in random variability with no area penalty. A 40-nm-node 0.248-μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit density to 2.98 Mb/mm2. MWC improved VDD_min@-6σ by 0.34 V and 0.22 V for read and write operations, respectively, enabling stable 1.0 V operations. Four nanosecond SRAM access time is achieved by adopting HCA, which cancels out a 1.4 ns increase of access delay caused by MWC.
Keywords :
CMOS memory circuits; SRAM chips; delays; memory architecture; hierarchical cell architecture; multistep word-line control technology; nanosecond SRAM access time; scaled-down high-density static random access memory; size 40 nm; time 1.4 ns; voltage 0.22 V; voltage 0.34 V; voltage 1.0 V; Computer architecture; Driver circuits; MOSFETs; Microprocessors; Random access memory; Voltage control; SRAM scaling; Static random access memory (SRAM); static noise margin; write margin;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2109434
