DocumentCode
146793
Title
Understanding system level caching behavior in multimedia SoC
Author
Karandikar, Prashant ; Mody, Mihir ; Sanghvi, Hetul ; Easwaran, Vasant ; Prithvi Shankar, Y.A. ; Gulati, Rishabh ; Nandan, Nibedita ; Mandal, Durbadal ; Das, S.
Author_Institution
Texas Instrum. India Pvt. Ltd., Bangalore, India
fYear
2014
fDate
3-5 April 2014
Firstpage
317
Lastpage
320
Abstract
A typical multimedia SoC consists of all or a subset of hardware components for image capture & processing, video compression and de-compression, computer vision, graphics and display processing. Each of these components access and compete for the limited bandwidth available in the shared external memory. Meeting latency (e.g., display) and throughput (e.g., video encode) is a critical problem to solve for such SoCs. In typical SoCs, this problem is solved using system level caches. However in this paper, we show results that indicate system level caches are not beneficial for multi-media traffic both in terms of DDR bandwidth savings as well as for latency reduction. We also show results of desirable features to improve multimedia performance in SoCs using a system cache.
Keywords
cache storage; multimedia communication; system-on-chip; DDR bandwidth savings; computer vision; display processing; graphics processing; image capture; image processing; latency reduction; multimedia SoC; multimedia performance; multimedia traffic; shared external memory; system level caches; video compression; Bandwidth; Indexes; System-on-chip; Cache replacement; Cache utilization; DDR; Display; Image; Latency; MB; Multimedia; Performance; SoC; Traffic; Video; use-case;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location
Melmaruvathur
Print_ISBN
978-1-4799-3357-0
Type
conf
DOI
10.1109/ICCSP.2014.6949853
Filename
6949853
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