DocumentCode :
146804
Title :
Low power architecture for motion compensation filter in a 4K Ultra HD video codec accelerator
Author :
Sanghvi, Hetul ; Nandan, Nibedita ; Mody, Mihir
Author_Institution :
Texas Instrum. Inc., Bangalore, India
fYear :
2014
fDate :
3-5 April 2014
Firstpage :
369
Lastpage :
372
Abstract :
Video codec accelerators in hand-held devices are driving the need for low power operation. Motion Compensation in a video codec performs interpolation on blocks of reference image if the motion-vectors refer to fractional pixel positions to form the prediction image for inter macro-blocks. In this paper, we present low power architecture for this motion compensation filter engine used in a 4K Ultra HD AVC accelerator. The paper presents an on-the-fly pixel padding approach without which the DDR bandwidth and power for the output frame in a decoder would have become worse by 9.4% for a full-HD operation. The paper also describes selective transpose - a novel approach to reduce filter engine computation and power. The whole filter engine dissipates less than 5 mW for 4K UHD decoder in a 28nm low power process.
Keywords :
filters; low-power electronics; motion compensation; video codecs; HD AVC accelerator; low power architecture; motion compensation filter; motion vectors; size 28 nm; ultrahigh definition video codec accelerator; Acceleration; Bandwidth; Decoding; Engines; Indexes; System-on-chip; AVC; DDR Bandwidth; H.264; Low Power; Motion Compensation; Transpose; Ultra HD;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location :
Melmaruvathur
Print_ISBN :
978-1-4799-3357-0
Type :
conf
DOI :
10.1109/ICCSP.2014.6949864
Filename :
6949864
Link To Document :
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