Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor

Author

Conway, Pat ; Kalyanasundharam, Nathan ; Donley, Gregg ; Lepak, Kevin ; Hughes, Bill

Author_Institution

Adv. Micro Devices, Sunnyvale, CA, USA

Volume

30

Issue

2

fYear

2010

Firstpage

16

Lastpage

29

Abstract

The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.

Keywords

cache storage; memory architecture; microprocessor chips; 12-core AMD Opteron processor; Magny Cours; blade servers; broadcast-based coherence; cache coherence protocol; cache hierarchy; memory latency; memory subsystem; server architecture; Bandwidth; Blades; Broadcasting; Computer architecture; Delay; Filters; Packaging; Probes; Protocols; Silicon; HyperTransport3 technology; blade server; cache; cache directory; memory hierarchy; multiprocessor; power envelopes; probe filter; processor; system interconnect; x86-64;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2010.31

Filename

5446248