DocumentCode :
1468509
Title :
Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture
Author :
Radosavljevic, P. ; Yuanbin Guo ; Cavallaro, J.R.
Author_Institution :
Patterson & Sheridan, LLP, Houston, TX, USA
Volume :
27
Issue :
8
fYear :
2009
fDate :
10/1/2009 12:00:00 AM
Firstpage :
1318
Lastpage :
1330
Abstract :
Iterative soft detection and channel decoding for MIMO OFDM downlink receivers is studied in this work. Proposed inner soft sphere detection employs a variable upper bound for number of candidates per transmit antenna and utilizes the breath-first candidate-search algorithm. Upper bounds are based on probability distribution of the number of candidates found inside the spherical region formed around the received symbolvector. Detection accuracy of unbounded breadth-first candidatesearch is preserved while significant reduction of the search latency and area cost is achieved. This probabilistically bounded candidate-search algorithm improves error-rate performance of non-probabilistically bounded soft sphere detection algorithms, while providing smaller detection latency with same hardware resources. Prototype architecture of soft sphere detector is synthesized on Xilinx FPGA and for an ASIC design. Using area-cost of a single soft sphere detector, a level of processing parallelism required to achieve targeted high data rates for future wireless systems (for example, 1 Gbps data rate) is determined.
Keywords :
MIMO communication; OFDM modulation; application specific integrated circuits; field programmable gate arrays; iterative methods; ASIC design; MIMO-OFDM receivers; Xilinx FPGA; bit rate 1 Gbit/s; breath-first candidate-search algorithm; channel decoding; iterative soft detection; probabilistically bounded soft sphere detection; probability distribution; search latency; system architecture; Delay; Detectors; Downlink; Iterative algorithms; Iterative decoding; MIMO; OFDM; Probability distribution; Transmitting antennas; Upper bound; Sphere detection, iterative detection-decoding, hardware implementation, FPGA prototype, ASIC synthesis, Gbps data throughput.;
fLanguage :
English
Journal_Title :
Selected Areas in Communications, IEEE Journal on
Publisher :
ieee
ISSN :
0733-8716
Type :
jour
DOI :
10.1109/JSAC.2009.091002
Filename :
5262288
Link To Document :
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