Scan-based BIST fault diagnosis

Existing built-in self-test (BIST) diagnostic techniques assume the existence of a few bit errors in a test response sequence. This assumption is unrealistic since in a BIST environment a single defect can usually cause hundreds or thousands of errors in a test response sequence. Without making the above assumption, this paper presents a novel BIST fault diagnostic technique for scan-based VLSI devices. Based on faulty signature information, our scheme guarantees correct identification of the scan flip-flops that capture errors during test, regardless of the number of errors the circuit may produce. In addition, it is able to identify failing test vectors with a better diagnostic capacity than existing techniques. The proposed scheme does not assume any specific fault model. Thus, it is applicable to all voltage-detectable faults. It also applies naturally to multifrequency BIST. This paper analyzes the efficiency of the scheme in terms of diagnostic coverage. Experimental results on several large ISCAS89 benchmark circuits and industrial circuits are also reported