DocumentCode
1469075
Title
A high-performance CMOS 32-bit parallel CRC engine
Author
Hobson, Richard F. ; Cheung, Keith L.
Author_Institution
Simon Fraser Univ., Burnaby, BC, Canada
Volume
34
Issue
2
fYear
1999
fDate
2/1/1999 12:00:00 AM
Firstpage
233
Lastpage
235
Abstract
Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented. In a 0.8-μm three-layer-metal CMOS process, the engine could handle about 5 Gbps data throughput. A compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. There are six gate delays plus a single-phase clock edge-triggered register
Keywords
CMOS logic circuits; error detection; integrated circuit layout; logic design; parallel processing; redundancy; 0.8 micron; 32 bit; 5 Gbit/s; binary tree reduction; compact layout; cyclic redundancy check generator engine; high-performance parallel CRC engine; predecoding; single-phase clock edge-triggered register; three-layer-metal CMOS process; Asynchronous transfer mode; CMOS process; CMOS technology; Circuits; Clocks; Cyclic redundancy check; Engines; Hardware; Polynomials; Routing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.743785
Filename
743785
Link To Document