Title :
A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance
Author :
Shrivastava, Mayank ; Baghini, Maryam Shojaei ; Sharma, Dinesh Kumar ; Rao, V. Ramgopal
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India
fDate :
6/1/2010 12:00:00 AM
Abstract :
For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.
Keywords :
MOSFET; silicon-on-insulator; thermal analysis; 3D device; bottom spacer FinFET structure; bottom spacer fin-shaped field-effect-transistor structure; electrothermal simulations; mixed-mode simulation; power dissipation; power-delay; self-heating behavior; short-channel performance; silicon-on-insulator FinFET; system-on-chip; thermal performance; CMOS logic circuits; CMOS technology; Circuit simulation; FETs; FinFETs; Logic devices; Power dissipation; Quantization; Space technology; System-on-a-chip; Bulk fin-shaped field-effect transistor (FinFET); electrothermal; fin-shaped field-effect transistor (FinFET); self-heating; short-channel performance; spacer; width quantization;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2010.2045686