Designing an average 8T SRAM

There is expansive use of SRAM memories in applications that have medium to low speed requirements, while having a very tight power budget. Due to this reason it has become critical to realize ultra-low-voltage and low-power SRAM designs. This can be achieved by operating the SRAM in sub/near threshold regime. Since the operation of the conventional 6T SRAM operation in the sub/near threshold regime shows poor functionality, several methods have been proposed to address the issues concerning this. The existing works in this field still are unable to overcome issues like data dependent leakage and stability of half selected cells. This work presents several circuit changes to effectively correct these issues through the proposed average 8T SRAM cell. The proposed SRAM cell is designed in 0.18 um CMOS technology. Eventually the proposed design performance is compared to the performance of the conventional 6T SRAM cell.