Low power DCT implementation approach for CMOS-based DSP processors

An algorithm is presented for the low power implementation of the discrete cosine transform on single multiplier CMOS DSPs. The algorithm reduces power by reducing the amount of switched capacitance within the multiplier section of the DSP. This is achieved by a combination of using shift operations where possible, and manipulating bit-correlation between successive cosine coefficients applied to the input of the multiplier section. It is shown with a number of examples that up to 50% power saving can be achieved and that the algorithm provides a potential for more savings in power