A Fully Fledged TDC Implemented in Field-Programmable Gate Arrays

Author

Wang, Jinhong ; Liu, Shubin ; Shen, Qi ; Li, Hao ; An, Qi

Author_Institution

Dept. of Modern Phys., Univ. of Sci. & Technol. of China, Hefei, China

Volume

57

Issue

2

fYear

2010

fDate

4/1/2010 12:00:00 AM

Firstpage

446

Lastpage

450

Abstract

The motivation of this paper is to implement a fully fledged time-to-digital converter (TDC) in a field-programmable gate array from Xilinx Virtex 4 family with self-test and temperature variation compensation features. The TDC resolution is temperature and supply voltage dependent which, to a large part, is compensated. A self-test procedure, which covers a temperature range of 30 Â°C to 60 Â°C is used to determine the compensation constants. After compensation and integral nonlinearity (INL) calibration, the TDC presents a timing resolution of 25 ps RMS or 50 ps per LSB. A total of 9 channels TDCs are implemented in a single FPGA.

Keywords

convertors; field programmable gate arrays; Xilinx Virtex 4 family; compensation constants; field-programmable gate arrays; fully fledged TDC implemented; integral nonlinearity calibration; self-test; supply voltage dependent; temperature 30 degC to 60 degC; temperature variation compensation; time-to-digital converter; Built-in self-test; Clocks; Counting circuits; Delay effects; Delay lines; Field programmable gate arrays; Interpolation; Temperature; Time measurement; Timing; Compensation; field-programmable gate arrays (FPGAs); time measurement; time-to-digital converter;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2009.2037958

Filename

5446507