• DocumentCode
    147034
  • Title

    Asynchronous successive approximation ADC for wireless applications in 180 nm CMOS technology

  • Author

    Varthini, K. Karthika ; Moni, D. Jackuline

  • Author_Institution
    Karunya Univ., Coimbatore, India
  • fYear
    2014
  • fDate
    3-5 April 2014
  • Firstpage
    1007
  • Lastpage
    1010
  • Abstract
    This paper describes an asynchronous successive approximation ADC. Six comparators are used for each conversion bit, clocked by a ripple clock which was generated after each comparison. Due to these six comparators feedback delay is eliminated. The SAR ADC is used for compact implementation, low power and high speed applications.
  • Keywords
    CMOS logic circuits; analogue-digital conversion; asynchronous circuits; comparators (circuits); logic design; ADC; CMOS; asynchronous successive approximation; comparators feedback delay; size 180 nm; Clocks; Latches; Reliability; Switches; Preamplifier with latch comparator; SA algorithm and bootstrap switch; analog to digital converter (ADC); asynchronous logic; binary weighted capacitive DAC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications and Signal Processing (ICCSP), 2014 International Conference on
  • Conference_Location
    Melmaruvathur
  • Print_ISBN
    978-1-4799-3357-0
  • Type

    conf

  • DOI
    10.1109/ICCSP.2014.6949998
  • Filename
    6949998
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=147034