CMOS quaternary latch

A new CMOS current-mode quaternary threshold logic latch circuit is presented. This circuit accepts and requantises quaternary logical currents during a SETUP clock mode and latches the input value during the HOLD clock mode. Using logical current increments of 10 mu A, the quaternary latch has been simulated to have a worst-case, three logic level transition, total SETUP and HOLD time of about 40 ns, and single level transition total SETUP and HOLD time of about 10 ns.