DocumentCode :
1470608
Title :
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
Author :
Metra, Cecilia ; Favalli, Michele ; Olivo, Piero ; Riccò, Bruno
Author_Institution :
Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
Volume :
16
Issue :
7
fYear :
1997
fDate :
7/1/1997 12:00:00 AM
Firstpage :
770
Lastpage :
776
Abstract :
This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples
Keywords :
CMOS logic circuits; built-in self test; combinational circuits; fault diagnosis; logic testing; CMOS self-checking circuit; bridging fault; combinational functional block; delay fault; electrical level design rule; on-line detection; parametric fault; CMOS logic circuits; Circuit faults; Clocks; Delay; Electrical fault detection; Error correction; Fault detection; Fault diagnosis; Logic testing; Voltage;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.644039
Filename :
644039
Link To Document :
بازگشت