Optimized reduced sample rate sigma-delta modulation

Author

Birru, Dagnachew

Author_Institution

Digital VLSI Sect., Philips Res. Lab., Eindhoven, Netherlands

Volume

44

Issue

11

fYear

1997

fDate

11/1/1997 12:00:00 AM

Firstpage

896

Lastpage

906

Abstract

An optimized reduced sample rate sigma-delta modulation technique for application in digital to analog conversion is presented. A general framework of a sigma-delta modulating topology where the major arithmetic computation is done at a rate of an integer fraction of the bit-stream rate Is proposed and analyzed. The effectiveness of the technique is illustrated using simulations of second- and third-order sigma-delta modulators. Its impact on modulator complexity, stability, and performance is discussed. Optimization techniques such as quadratic programming are utilized in choosing proper filter coefficients

Keywords

digital-analogue conversion; quadratic programming; sigma-delta modulation; signal sampling; arithmetic computation; bit-stream rate; complexity; digital to analog conversion; filter coefficients; integer fraction; noise shaping; optimization; performance; quadratic programming; sample rate; sigma-delta modulation; simulation; stability; topology; CMOS logic circuits; Circuit noise; Circuit topology; Delta-sigma modulation; Frequency; Noise reduction; Noise shaping; Quantization; Sampling methods; Signal to noise ratio;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.644043

Filename

644043