VLSI implementation of low -complexity Reed Solomon decoder

Author

Mhaske, Samir D. ; Ghodeswar, Ujwala ; Sarate, G.G.

Author_Institution

Yeshwantrao Chavan Coll. of Eng., Rashtrasant Tukadoji Maharaj Nagpur Univ., Nagpur, India

fYear

2014

fDate

3-5 April 2014

Firstpage

1214

Lastpage

1217

Abstract

In this paper, a low complexity architecture of Reed-Solomon (RS) code is developed to correct errors based on truncated inversion less Berlekamp-Massey algorithm. The arithmetic operations which are used in RS code are Galois Fields (GF) addition and multiplication. This paper presents: i) RS encoder modeled using MATLAB with data encoded in the noisy channel for functional verification. ii) RS decoder modeled in Verilog HDL to recover the erroneous data. The Verilog modeled RS (255, 239) decoder has the capability of 8 symbol-errors detection and correction. The proposed decoder has been designed and synthesized for the Xilinx Spartan6 series FPGAs xc6lx16-3. The resource consumption is about 44%, and the data processing rates over 1.3Gbit/s is realized.

Keywords

Reed-Solomon codes; VLSI; codecs; field programmable gate arrays; Berlekamp-Massey algorithm; FPGA; Galois fields; MATLAB; RS code; Reed Solomon decoder; Reed-Solomon code; VLSI; Verilog HDL; Verilog modeled RS decoder; Xilinx Spartan6 series; bit rate 1.3 Gbit/s; data processing; resource consumption; Computational modeling; Decoding; Equations; Hardware design languages; MATLAB; Mathematical model; Silicon; Berlekamp-Massey algorithm; Reed-Solomon codes; key equation solver; syndrome;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Signal Processing (ICCSP), 2014 International Conference on

Conference_Location

Melmaruvathur

Print_ISBN

978-1-4799-3357-0

Type

conf

DOI

10.1109/ICCSP.2014.6950044

Filename

6950044