DocumentCode :
1471383
Title :
Learning as applied to stochastic optimization for standard-cell placement
Author :
Su, Lixin ; Buntine, Wray ; Newton, A. Richard ; Peters, Bradley S.
Author_Institution :
Transmeta Corp., Santa Clara, CA, USA
Volume :
20
Issue :
4
fYear :
2001
fDate :
4/1/2001 12:00:00 AM
Firstpage :
516
Lastpage :
527
Abstract :
Stochastic combinatorial optimization techniques, such as simulated annealing and genetic algorithms, have become increasingly important in design automation as the size of design problems have grown and the design objectives have become increasingly complex. However, stochastic algorithms are, often slow since a large number of random design perturbations are required to achieve an acceptable result-they have no built-in “intelligence”. In this paper, it is shown that statistical learning techniques can improve the quality of results and reduce the number of expensive cost-function evaluations for stochastic optimization for a particular solution quality. In particular, simulated annealing was selected as a representative stochastic optimization approach and a two-dimensional cell-based layout placement problem was used to evaluate the utility of such a learning-based approach. In this paper, we used regression to learn the properties of the solution space and tested the trained algorithm on a number of examples to demonstrate the improvement gained. A general response model is constructed by learning from the annealing of benchmark circuits. This model is then used in the trained simulated annealing, which returns significantly better annealing quality than the untrained algorithm for the same number of moves in the solution space. The annealing quality improvement was 15%-43% for the set of examples used in training and 7%-21% when the trained algorithm was applied to new examples
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; learning (artificial intelligence); simulated annealing; statistical analysis; stochastic processes; 2D cell-based layout placement problem; VLSI layout; cost-function evaluations reduction; floorplanning; general response model; linear regression; simulated annealing; standard-cell placement; statistical learning techniques; stochastic algorithms; stochastic optimization; windowed sampling technique; Algorithm design and analysis; Benchmark testing; Circuit simulation; Circuit testing; Design automation; Design optimization; Genetic algorithms; Simulated annealing; Statistical learning; Stochastic processes;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.918210
Filename :
918210
Link To Document :
بازگشت