Title :
Bit-fixing in pseudorandom sequences for scan BIST
Author :
Touba, Nur A. ; McCluskey, Edward J.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
fDate :
4/1/2001 12:00:00 AM
Abstract :
A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR´s serial output to “fix” certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation
Keywords :
automatic test pattern generation; binary sequences; built-in self test; design for testability; digital integrated circuits; integrated circuit testing; logic testing; DFT; LFSR; automatic test pattern generation procedure; bit-fixing; built-in self test; complete fault coverage; correlating ATPG procedure; deterministic test cubes; linear feedback shift register; low-overhead scheme; pseudorandom sequences; random-pattern-resistant faults; scan BIST; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Degradation; Electrical fault detection; Fault detection; Logic testing; Random sequences; System performance;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
