Title :
A parallel video converter for displaying 4:3 images on 16:9 HDTV receivers
Author :
Hsia, Shih-Chang ; Liu, Bin-Da ; Yang, Jar-Fen ; Huang, Chien-Hsiu
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
12/1/1996 12:00:00 AM
Abstract :
The 16/9 widescreen TV is becoming popular in the marketplace; however, its aspect ratio is not compatible with the conventional 4/3 SDTV program. We propose a nonuniform conversion to efficiently display 4/3 SDTV programs on a 16/9 high-definition television (HDTV) monitor, for real time HDTV receivers, a parallel video converter is also proposed using nonuniform interpolation. To trade off complexity and performance, we only use one field-memory and one line-buffer for motion adaptation to interpolate the pixels, which can be finished by the parallel computation kernel in one clock cycle. In order to combine parallel computation, the memory-slice method is employed, which is efficiently controlled by a state machine for nonuniform interpolation. With parallel conversion, a high-speed video converter can be achieved for advanced HDTV receivers
Keywords :
buffer storage; convertors; high definition television; interpolation; parallel processing; television receivers; video equipment; video signal processing; 16/9 high-definition television monitor; 16/9 widescreen TV; 16:9 HDTV receivers; 4/3 SDTV program; 4:3 image display; aspect ratio; clock cycle; field-memory; high-speed video converter; line-buffer; memory-slice method; motion adaptation; nonuniform conversion; nonuniform interpolation; parallel computation; parallel computation kernel; parallel video converter; performance; pixels interpolation; state machine; Clocks; Concurrent computing; Displays; HDTV; High definition video; Image converters; Interpolation; Kernel; Monitoring; TV receivers;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
