Vertical N-channel MOSFETs for extremely high density memories: the impact of interface orientation on device performance

We investigate vertical n-channel MOSFETs fabricated at the sidewalls of etched trenches. In general, these sidewalls can be nonplanar and incorporate different crystallographic orientations. Therefore, it is necessary to involve models for a variety of interface orientations in order to describe scaled-down vertical devices. However, the crystallographic orientation of the interface has a strong impact on crucial device parameters such as gate oxide thickness, carrier mobility, and interface trap density. For the first time, in this work a complete set of these parameters is investigated systematically for a wide range of different crystallographic orientations. Based on these parameters, the modeling of vertical MOSFETs featuring a cylindrical geometry is demonstrated and verified by measurements. Furthermore, differences observed between vertical and planar devices of equal parameters are deduced from interface properties related to the orientation of the sidewall