Title :
1/f noise in CMOS transistors for analog applications
Author :
Nemirovsky, Yael ; Brouk, Igor ; Jakobson, Claudio G.
Author_Institution :
Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
fDate :
5/1/2001 12:00:00 AM
Abstract :
Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits
Keywords :
1/f noise; CMOS analogue integrated circuits; MOSFET; flicker noise; integrated circuit design; integrated circuit modelling; semiconductor device models; semiconductor device noise; 0.5 μm technology; 0.5 mum; 1/f noise; 2 μm technology; 2 mum; CMOS analog circuits; CMOS transistors; NMOS transistors; PMOS transistors; SPICE models; analog applications; drain current 1/f noise; flicker noise coefficient; input referred noise; low noise CMOS processes; model; optimized processing; power spectral density; saturation; subthreshold; wide bias conditions; Analog circuits; CMOS analog integrated circuits; CMOS process; CMOS technology; Circuit noise; MOSFETs; Noise measurement; Noise reduction; SPICE; Semiconductor device modeling;
Journal_Title :
Electron Devices, IEEE Transactions on
