Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

Author

Seah, Siau Hing Lionel ; Yeo, Kiat Seng ; Jian Guo Fia ; Do, Manh Anh

Author_Institution

Sch. of Electr. & Electronic. Eng., Nanyang Technol. Inst., Singapore

Volume

48

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

1001

Lastpage

1004

Abstract

The effective channel length L_eff and total external series resistance R_TOText of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the L_eff and R_TOText extraction routine is discussed. The proposed models have been verified for temperature ranging from 223 K to 398 K and source-to-body voltage V_SB>0 V conditions

Keywords

BIMOS integrated circuits; MOSFET; electric resistance; semiconductor device models; 223 to 398 K; Bi-MOS hybrid-mode environment; bias dependence; device threshold voltage; effective channel length; model; scaled LDD pMOSFETs; source-to-body voltage conditions; temperature dependence; total external series resistance; Data mining; Energy states; Hybrid junctions; Immune system; Implants; MOSFETs; Temperature distribution; Thickness measurement; Threshold voltage; Vibration measurement;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.918250

Filename

918250