Title :
The nonvolatile cell hidden in standard CMOS logic technologies
Author :
Lovett, Simon J.
Author_Institution :
Cypress Semicond., San Jose, CA, USA
fDate :
5/1/2001 12:00:00 AM
Abstract :
An electrically programmable cell is described which is latently available in virtually all modern CMOS logic processes. The cell consists of an n-ch and a p-ch device with their gates coupled together to form the floating gate. The element may be used to adjust circuit function, timing, zero adjust, etc
Keywords :
CMOS logic circuits; programmable circuits; timing; 0.25 mum; 3.3 V; CMOS logic technologies; circuit function; coupled gates; electrically programmable cell; floating gate; hidden nonvolatile cell; n-ch device; one time programmable nonvolatile cell; p-ch device; timing; zero adjust; Breakdown voltage; CMOS logic circuits; CMOS process; CMOS technology; Costs; EPROM; Electric breakdown; Logic devices; Substrates; Tunneling;
Journal_Title :
Electron Devices, IEEE Transactions on
