A high speed proficient power reduction method using clustering based flip flop merging

In today´s electronic scenario, low power has grasped attention. The ought for low power has been a main epitome whereby the power dissipation is one of the constraint as with performance and area. In the past, the major apprehension of the VLSI designer are its area, performance, cost, reliability but now, the power obsessive is mainly due to clocking for the circuit that incorporate deeply scaled CMOS technology. Eliminating redundant inverter in merging out one bit flip flops into multi bit causes optimization in wirelength which would probably result in reduction of power. Its been a successful power saving methodology whose dynamic power of clock and total flip flop area is effectively encapsulated. In this paper, an agglomerative clustering algorithm is utilized to obtain nearest clustering for merging flip flops. The multi bit technique is introduced in fir circuit to lessen power as well as area. This satisfies with the above given constraints. According to the experimental results, our algorithm considerably reduces clock power by 21.98% and it is found that total gate count is reduced from 264 to 148 which increases the speed thus reducing the delay.