A low power architecture for H.264 encoder in Intra Prediction Mode

H.264 requires large number of computational elements due to their computational complexity. By reducing this computational complexity the low power architecture is proposed in this paper. In this work the computational reduction using Pixel similarity computation and the Minimum SAD computation is proposed. The output of pixel similarity computation reduces the number of comparisons between current block pixels and the neighboring block pixels in Intra Prediction Mode. As a result the computational complexity in terms of additions and multiplications are reduced in the design of encoder and consequently the power consumption is also reduced. In this work the 4×4 luma block is taken into account for the pixel comparison and residual prediction. The power consumption for the architecture is reduced by 22.77%. The architecture is implemented in Verilog. The RTL for the Verilog code is verified in Virtex5 XC5VLX50T FPGA.