DocumentCode :
1472086
Title :
Area scaling analysis of CMOS ADCs
Author :
Verhelst, Marian ; Murmann, Boris
Author_Institution :
MICAS-ESAT-KULeuven, Heverlee, Belgium
Volume :
48
Issue :
6
fYear :
2012
Firstpage :
314
Lastpage :
315
Abstract :
Recently, the continuing reduction of analogue-to-digital converter (ADC) power consumption has received a lot of attention in the literature, while it is often assumed that converter area does not scale well anymore. An area scaling analysis based on historical data is performed. It is shown that ADC area scaling has been alive and well across all ADC topologies, and for both matching and noise-limited ADCs.
Keywords :
CMOS integrated circuits; analogue-digital conversion; network topology; power consumption; ADC area scaling; ADC topologies; CMOS ADC; analogue-to-digital converter; area scaling analysis; matching ADC; noise-limited ADC; power consumption;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2012.0253
Filename :
6171018
Link To Document :
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