DocumentCode :
1472409
Title :
An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm
Author :
Hsu, Jah-Ming ; Wang, Chin-Liang
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
7
Issue :
6
fYear :
1997
fDate :
12/1/1997 12:00:00 AM
Firstpage :
864
Lastpage :
871
Abstract :
Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital data against errors occurring in the transmission process. Since the decoding process for RS codes is rather computation-extensive, special-purpose hardware structures are often necessary for it to meet the real-time requirements. In this paper, an area-efficient pipelined very large scale integration (VLSI) architecture is proposed for RS decoding. The architecture is developed based on a time domain algorithm using the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder can process one data block every n clock cycles, i.e., the average decoding rate is one symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency
Keywords :
Reed-Solomon codes; VLSI; decoding; digital signal processing chips; error correction codes; pipeline processing; time-domain analysis; RS codes; Reed-Solomon codes; area-efficient pipelined VLSI architecture; communication systems; decoding; digital data; error protection; hardware complexity; latency; remainder decoding; special-purpose hardware structures; t-error-correcting RS code; time domain algorithm; time-domain algorithm; transmission process; Clocks; Computational complexity; Computer architecture; Frequency estimation; HDTV; Hardware; Iterative decoding; Signal processing algorithms; Time domain analysis; Very large scale integration;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/76.644066
Filename :
644066
Link To Document :
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