Title :
Efficient implementation of memory controllers and memories and virtual platform
Author :
Radha Devi, D.V.D. ; Kondugari, Praveen Kumar ; Basavaraju, G. ; Gangadharaiah, S.L.
Author_Institution :
M.S. Ramaiah Inst. of Technol., Bangalore, India
Abstract :
Virtual Platforms, SystemC[1] Simulations for SoCs (System on Chip) is one of the prominent technologies´ which is widely used today in the industry for early software development despite hardware availability. SystemC facilitates development of Transaction-Level Models (TLMs)[2][3] for SoC components at higher level of abstraction than RTL. This enables lower modeling effort and higher simulation speeds. Memories and Memory Controllers play significant role in the SoC Architecture right from boot-up of the SoC to the regular functionalities. With the growing complexity of SoC Architecture, SoC comprises different kind of memories and Controllers. All though the access timing, electrical levels, technology, access commands are different for each of the memories, when it comes to simulation model features like electrical levels, technology used etc. are of no impact. If the Simulation abstraction is functional accurate type which is generally used for software development use-case, as the software has no idea on cycle information even the accuracy in memory access timings are not of much significance. Features like interface & interface protocols between controller and memories, state machine synchronization, commands and formats for page programming, page reading, block erasing, pipeline accessing, parameter page reading, error control correction etc. are to be implemented functionally accurate. Considering the increasing number of features and complexity of the Flash Memories and Memory Controllers, the effort involved in developing SystemC TLM models for these is significant and many a time repetitive across different memory models and controllers. One of the challenges in this project is to come up with design solutions for implementing Flash Memories and Memory Controllers which would reduce model development efforts and afford reusability, and secondly to improve the memory accessing time of the implemented memories which in turn to- improve simulation speeds a buy-in factor for the customers/simulation users.
Keywords :
flash memories; hardware description languages; memory architecture; paged storage; system-on-chip; SoC architecture; SoC components; SystemC TLM models; SystemC simulations; access commands; block erasing; electrical levels; error control correction; flash memories; hardware availability; interface & interface protocols; memory access timings; memory accessing time; memory controllers; memory models; page programming; parameter page reading; pipeline accessing; regular functionalities; simulation abstraction; software development use-case; state machine synchronization; system on chip; transaction-level models; virtual platform; Accuracy; Hardware; Software; Testing; Time-domain analysis; Time-varying systems; Timing; Memory Controller Model; Memory Model; Simulation; SoC; SystemC; Virtual Platforms;
Conference_Titel :
Communications and Signal Processing (ICCSP), 2014 International Conference on
Conference_Location :
Melmaruvathur
Print_ISBN :
978-1-4799-3357-0
DOI :
10.1109/ICCSP.2014.6950127