Title :
A VLSI architecture for real-time edge linking
Author :
Hajjar, Amjad ; Chen, Tom
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
fDate :
1/1/1999 12:00:00 AM
Abstract :
A real-time algorithm and its VLSI implementation for edge linking is presented. The linking process is based on the break points´ directions and the weak level points. The proposed VLSI architecture is capable of outputting one pixel of the linked edge map per clock cycle with a latency of 11n+12 clock cycles, where n is the number of pixel columns in the image
Keywords :
CMOS integrated circuits; VLSI; edge detection; object recognition; VLSI architecture; break points´ directions; real-time edge linking; weak level points; Clocks; Delay; Detectors; Humans; Image edge detection; Image processing; Joining processes; Object recognition; Pixel; Very large scale integration;
Journal_Title :
Pattern Analysis and Machine Intelligence, IEEE Transactions on
