Title :
Bit-serial modular multiplier
Author_Institution :
Dept of Electr. Eng., Edinburgh Univ., UK
Abstract :
A bit-serial modular multiplier is presented which uses a table look-up method to perform modular reduction. Since the clock frequency is independent of word length this design is most useful when dealing with large integers, and is required by many modern cryptographic systems.
Keywords :
application specific integrated circuits; cryptography; digital arithmetic; digital integrated circuits; multiplying circuits; bit-serial modular multiplier; clock frequency; cryptographic systems; large integers; modular reduction; table look-up method; word length;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19891115
