VLSI implementation of locally connected neural network for solving partial differential equations

Author

Yentis, Richard, Jr. ; Zaghloul, M.E.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., George Washington Univ., Washington, DC, USA

Volume

43

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

687

Lastpage

690

Abstract

This brief presents a locally connected neural network for solving a class of partial differential equations. Each neural cell is designed using active and passive components. An architecture is described to control the weights between the neurons. The major benefit of the architecture is that it does not require additional space outside of the cell for routing the control lines no matter how many cells are used. The CMOS VLSI implementation of a sixteen cell network was fabricated and measured. The results of this network are compared to the numerical solution of the partial differential equations

Keywords

CMOS analogue integrated circuits; VLSI; neural chips; neural net architecture; partial differential equations; CMOS VLSI; active components; architecture; locally connected neural network; numerical solution; partial differential equations; passive components; Cellular neural networks; Circuits; Finite difference methods; Neural networks; Neurons; Partial differential equations; Poisson equations; Routing; Very large scale integration; Weight control;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.526685

Filename

526685