Investigation of interface traps in LDD pMOST´s by the DCIV method

Author

Jie, B.B. ; Li, M.-F. ; Lou, C.L. ; Chim, W.K. ; Chan, D.S.H. ; Lo, K.F.

Author_Institution

Fac. of Eng., Nat. Univ. of Singapore, Singapore

Volume

18

Issue

12

fYear

1997

Firstpage

583

Lastpage

585

Abstract

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high.

Keywords

MOSFET; electric current measurement; electron traps; hot carriers; interface states; semiconductor device reliability; semiconductor device testing; 0.6 mum; DCIV method; LDD pMOST; LDD region; channel hot-carrier stress conditions; channel region; direct-current current-voltage technique; electron trapping; hot electron injection; hot-carrier degradation; interface trap spatial location; interface traps; reliability; stress conditions; stressing gate voltage; submicron buried-channel LDD pMOSTs; Current measurement; DC generators; Degradation; Electron traps; FETs; Hot carriers; Low voltage; Radiative recombination; Secondary generated hot electron injection; Stress;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.644078

Filename

644078