Title :
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus
Author :
Zerbe, Jared L. ; Chau, Pak S. ; Werner, Carl W. ; Thrush, Timothy P. ; Liaw, H.J. ; Garlepp, Bruno W. ; Donnelly, Kevin S.
Author_Institution :
Rambus Inc., Los Altos, CA, USA
fDate :
5/1/2001 12:00:00 AM
Abstract :
A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-μm CMOS and tested in a 28-Ω evaluation system using on-chip 210 pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices
Keywords :
Gray codes; preamplifiers; printed circuit layout; pulse amplitude modulation; receivers; timing; 0.35 micron; 1.6 Gbit/s; 4-PAM signaling; Gray coding; LSB input receiver; area; current-mode signaling; folded preamplifier architecture; high-gain windowed integrating input receiver; multidrop bus; power; pseudorandom bit sequence; pulse-amplitude-modulated signalling system; signal-to-noise ratio; slave devices; system voltage; timing shmoos; transmitter structures; Bandwidth; Circuit testing; Communication system signaling; Pins; Semiconductor device measurement; Signal design; Signal to noise ratio; System testing; System-on-a-chip; Transmitters;
Journal_Title :
Solid-State Circuits, IEEE Journal of
