A dual-loop delay-locked loop using multiple voltage-controlled delay lines

Author

Jung, Yeon-Jae ; Lee, Seung-Wook ; Shim, Daeyun ; Kim, Wonchan ; Kim, Changhyun ; Cho, Soo-In

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

36

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

784

Lastpage

791

Abstract

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-μm CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV

Keywords

CMOS digital integrated circuits; clocks; delay lines; delay lock loops; 0.25 micron; 2.5 V; 400 MHz; CMOS process; dual-loop delay-locked loop; duty cycle corrector; quadrature clock; replica biasing circuit; voltage-controlled delay line; CMOS process; Circuit testing; Clocks; Delay effects; Delay lines; Frequency synchronization; Jitter; Phase locked loops; Pulse generation; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.918916

Filename

918916