A clock distribution network for microprocessors

Author

Restle, Phillip J. ; McNamara, Timothy G. ; Webber, David A. ; Camporese, Peter J. ; Eng, Kwok F. ; Jenkins, Keith A. ; Allen, David H. ; Rohn, Michael J. ; Quaranta, Michael P. ; Boerstler, David W. ; Alpert, Charles J. ; Carter, Craig A. ; Bailey, Roger

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

36

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

792

Lastpage

799

Abstract

A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured

Keywords

circuit tuning; clocks; microprocessor chips; buffered tree network topology; circuit tuning; clock distribution network; interconnect grid; microprocessor chip; Capacitors; Clocks; Delay; Distribution strategy; Frequency; Inductors; Microprocessor chips; Network topology; Resistors; Wire;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.918917

Filename

918917