Title :
A 5.2-GHz CMOS receiver with 62-dB image rejection
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fDate :
5/1/2001 12:00:00 AM
Abstract :
A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-μm digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP3 of -15 dBm, and a voltage conversion gain of 43 dB, while draining 29 mW from a 2.5-V supply
Keywords :
CMOS analogue integrated circuits; flicker noise; heterodyne detection; integrated circuit noise; radio receivers; 0.25 micron; 2.5 V; 29 mW; 43 dB; 5.2 GHz; 6.4 dB; CMOS receiver; IP3; RF communication system; baseband amplifier; double downconversion heterodyne architecture; flicker noise; image rejection; local oscillator; mixer; noise figure; offset cancellation; voltage conversion gain; 1f noise; Baseband; CMOS digital integrated circuits; CMOS technology; Frequency; Gain; Image converters; Local oscillators; Noise figure; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
