Space compaction under generalized mergeability

Author

Das, Sunil R. ; Petriu, Emil M. ; Barakat, Tony F. ; Assaf, Mansour H. ; Nayak, Amiya R.

Author_Institution

Dept. of Electr. Eng., Ottawa Univ., Ont., Canada

Volume

47

Issue

5

fYear

1998

fDate

10/1/1998 12:00:00 AM

Firstpage

1283

Lastpage

1293

Abstract

Generalized mergeability criteria for merging an arbitrary number of output sequences have been established under conditions of stochastic dependence and independence of line errors. In this paper, the authors report experimental results on ISCAS 85 benchmark circuits which were targeted for space compaction using these generalized mergeability criteria

Keywords

VLSI; automatic test pattern generation; built-in self test; circuit complexity; combinational circuits; data compression; fault simulation; integrated circuit testing; logic simulation; merging; sequences; AND gates; ATALANTA; BIST; COMPACTEST; FSIM; ISCAS 85 benchmark circuits; OR gates; XOR gates; arbitrary number of output sequences; combinational circuits; fault simulation; generalized mergeability criteria; line errors; logic function; logic simulation; pseudorandom test sets; space compaction; stochastic dependence; stochastic independence; test sequences; tree structure; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Logic testing; Merging; Space technology; Stochastic processes; Very large scale integration;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.746598

Filename

746598