Ta/sub 2/O/sub 5//silicon barrier height measured from MOSFETs fabricated with Ta/sub 2/O/sub 5/ gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta/sub 2/O/sub 5/ gate dielectric were fabricated. The Ta/sub 2/O/sub 5//silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I/sub g//I/sub d/) versus ln(I/sub sub//I/sub d/) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta/sub 2/O/sub 5/ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V.