DocumentCode :
1474816
Title :
Alpha 21164 testability strategy
Author :
Bhavsar, Dilip K. ; Edmondson, John H.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Volume :
14
Issue :
1
fYear :
1997
Firstpage :
25
Lastpage :
33
Abstract :
A custom DFT strategy solved specific testability and manufacturing issues for this high performance microprocessor. Hardware and software assisted self test and self repair features helped meet aggressive schedule and manufacturing quality and cost goals
Keywords :
built-in self test; computer testing; design for testability; integrated circuit manufacture; integrated circuit testing; Alpha 21164 testability strategy; cost goals; custom DFT strategy; high performance microprocessor; manufacturing issues; manufacturing quality; self repair features; software assisted self test; CMOS logic circuits; Costs; Frequency estimation; Logic arrays; Logic testing; Manufacturing; Microprocessors; Pipelines; Read-write memory; Registers;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.573357
Filename :
573357
Link To Document :
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