• DocumentCode
    1474849
  • Title

    Collateral ASIC test

  • Author

    Bailey, Al ; Lada, Tim ; Preston, Jim

  • Author_Institution
    Alcatel Network Syst., MS, USA
  • Volume
    14
  • Issue
    1
  • fYear
    1997
  • Firstpage
    55
  • Lastpage
    63
  • Abstract
    Boundary scan techniques fall short in testing ASICs embedded in printed-board assemblies. By providing a new interconnect, this technique extends the benefits of boundary scan to ASICs whether they incorporate the Bscan interface or not
  • Keywords
    application specific integrated circuits; integrated circuit testing; ASICs; boundary scan; printed-board assemblies; testing ASICs; Application specific integrated circuits; Assembly; Built-in self-test; Circuit testing; Clocks; Integrated circuit interconnections; Logic circuits; Logic design; Logic testing; Multiplexing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.573368
  • Filename
    573368
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1474849