Title :
Fusing Internet Protocol (IP) receive module at receiving path of open TCP/IP custom Single-Purpose Processor
Author :
Amiri, Rami ; Elkeelany, Omar
Author_Institution :
Dept. of Electr. & Comput. Eng., Tennessee Technol. Univ., Cookeville, TN, USA
Abstract :
In this research work, Internet Protocol (IP ) receive module is proposed to represent the IP layer at receiving path of an open TCP/IP custom single-purpose processor. Main components of IP receive module architecture and Finite-State Machine (FSM) are designed at Register Transfer Level (RTL) using VHDL language. Design and synthesis verification results are depicted using SignalTab logic analyzer.
Keywords :
Internet; finite state machines; hardware description languages; logic design; microprocessor chips; transport protocols; FSM; IP layer; IP receive module; IP receive module architecture; Internet protocol receive module; RTL; SignalTab logic analyzer; VHDL language; design verification; finite-state machine; open TCP-IP custom single-purpose processor; receiving path; register transfer level; synthesis verification; Clocks; Computer architecture; IP networks; Internet; Protocols; Random access memory; Writing; OSI model; Triple-Speed Ethernet;
Conference_Titel :
SOUTHEASTCON 2014, IEEE
Conference_Location :
Lexington, KY
DOI :
10.1109/SECON.2014.6950650
