Superconducting latching/SFQ hybrid RAM

Author

Nagasawa, Shuichi ; Hasegawa, Haruhiro ; Hashimoto, Tatsunori ; Suzuki, Hideo ; Miyahara, Kazunori ; Enomoto, Youichi

Author_Institution

Supercond. Res. Lab., ISTEC, Tokyo, Japan

Volume

11

Issue

1

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

533

Lastpage

536

Abstract

We have developed a 256-bit superconducting latching/SFQ hybrid (SLASH) RAM block as the first step in developing a 16-Kbit SLASH RAM, which enables high-frequency clock operation up to 10 GHz. The SLASH RAM is composed of ac-powered latching devices and dc-powered SFQ devices. The 256-bit SLASH RAM block is composed of 16×16 matrix array of vortex transitional memory cells, SFQ-NOR decoders, latching drivers, latching sense circuits, and address buffers. The 256-bit SLASH RAM block chips were fabricated and tested. We confirmed that the 256-bit SLASH RAM block functioned successfully

Keywords

random-access storage; superconducting arrays; superconducting memory circuits; 10 GHz; 256 bit; Josephson junction; SFQ-NOR decoder; SLASH RAM; address buffer; latching driver; latching sense circuit; superconducting latching/SFQ hybrid RAM; vortex transitional memory cell array; Circuit testing; Clocks; Decoding; Digital systems; Driver circuits; Frequency; Impedance; Latches; Random access memory; Read-write memory;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.919400

Filename

919400