DocumentCode
1475597
Title
An effective memory addressing scheme for FFT processors
Author
Ma, Yutai
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
Volume
47
Issue
3
fYear
1999
fDate
3/1/1999 12:00:00 AM
Firstpage
907
Lastpage
911
Abstract
The memory organization of FFT processors is considered. The new memory addressing assignment allows simultaneous access to all the data needed for butterfly calculations. The advantage of this memory addressing scheme lies in the fact that it reduces the delay of address generation nearly by half compared to existing ones
Keywords
delays; digital signal processing chips; fast Fourier transforms; hypercube networks; pipeline arithmetic; storage allocation; FFT processors; address generation delay; butterfly calculations; effective memory addressing scheme; memory addressing assignment; memory organization; Added delay; Circuits; Discrete cosine transforms; Discrete transforms; Fast Fourier transforms; Flow graphs; Hardware; Read only memory; Signal processing algorithms; Speech processing;
fLanguage
English
Journal_Title
Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1053-587X
Type
jour
DOI
10.1109/78.747802
Filename
747802
Link To Document