DocumentCode :
1475627
Title :
On ATPG for Multiple Aggressor Crosstalk Faults
Author :
Ganeshpure, Kunal ; Kundu, Sandip
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA
Volume :
29
Issue :
5
fYear :
2010
fDate :
5/1/2010 12:00:00 AM
Firstpage :
774
Lastpage :
787
Abstract :
Crosstalk faults have emerged as a significant mechanism of circuit failure due to decreasing process geometries and increasing operation frequencies. Long signal nets are highly susceptible to crosstalk faults because they tend to have a higher coupling capacitance to overall capacitance ratio. Moreover, a typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk induced delay on a victim net, it may be impossible to activate all aggressors logically or simultaneously to constructively induce maximum noise at the victim. Therefore, pattern generation must focus on activating a maximal subset of aggressors, weighted by actual coupling capacitance value, in close temporal proximity of the victim net transition. This max-satisfiability problem is constrained by fault effect propagation condition which involves determining an input signal assignment so as to propagate the fault effect at the victim to the primary output. In this paper, we present Automatic Test Pattern Generation (ATPG) solutions for multiple aggressor crosstalk faults for zero and unit delay models and compare the magnitude of crosstalk induced delay at the victim net. Our solution involves a combination of 0-1 Integer Linear Programming (ILP), for maximal aggressor excitation. Fault effect propagation is solved independently by using traditional stuck-at fault ATPG or by generating additional ILP constraints thus forming a integrated ILP formulation with error propagation. The effect of gate delays is summed by circuit transformation. The proposed technique was applied to ISCAS85 benchmark circuits. Results indicate that the percentage of total capacitance that can be switched varies from 75-100% for zero delay and 30-80% for variable delay case while achieving propagation of the fault effect to primary output.
Keywords :
automatic test pattern generation; crosstalk; fault diagnosis; integer programming; linear programming; 0-1 integer linear programming; ATPG; ISCAS85 benchmark circuits; automatic test pattern generation; circuit failure; error propagation; fault effect propagation condition; high coupling capacitance; input signal assignment; max-satisfiability problem; multiple aggressor crosstalk faults; pattern generation; unit delay models; victim net transition; Automatic test pattern generation; Capacitance; Circuit faults; Coupling circuits; Crosstalk; Delay effects; Frequency; Geometry; Noise generators; Propagation delay; Circuit partitioning; fault effect propagation; integer linear programming; multiple aggressor crosstalk faults; stuck-at fault ATPG;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2010.2043589
Filename :
5452112
Link To Document :
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