Improved methods for yield-optimization of digital logic

Yield optimization remains the primary device-level design task in digital superconductor electronics. We discuss yield-optimization in the context of our particular software implementation, Malt2, which interfaces to the circuit simulator Spice. This version contains significant improvements both to the numerical algorithms and in ease of use. Two special algorithms of yield-optimization are extant, both of which map out the multidimensional operating region of the circuit and center parameters within the operating region. We describe modifications to these methods that make them practical. The greatest improvement to usability is a new method of defining correct circuit operation; an envelope is defined around each Spice-generated waveform based on two parameters that describe acceptable time and level uncertainty. The envelope can be applied to arbitrary waveforms and can be represented graphically. The features and algorithms of Malt2 are illustrated with circuit examples. Finally, we describe the role of yield optimization within the larger context of a complete design methodology and tool set