• DocumentCode
    1476710
  • Title

    Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees

  • Author

    Celik, Mustafa ; Pileggi, Lawrence T.

  • Author_Institution
    Monterey Design Syst., Sunnyvale, CA, USA
  • Volume
    18
  • Issue
    3
  • fYear
    1999
  • fDate
    3/1/1999 12:00:00 AM
  • Firstpage
    293
  • Lastpage
    300
  • Abstract
    As IC clock frequencies approach the GHz range, the distribution of the clock signals becomes more critical in terms of controlling both skew and signal attenuation. Moreover, inductance effects are evident since RC transmission lines will overly attenuate these high-frequency clock signals. To facilitate accurate optimization of clock tree performance and skew requires simple metrics which capture these high-frequency effects. In this paper, we derive simple metrics and bounds for the phase delay and the attenuation of a periodic [RC(L)] tree response as a function of the fundamental frequency of the clock signal. These metrics are based on the first two moments of the impulse response, and are shown to further provide a mechanism for control of underdamped responses (reflections). An important result of this work is the clear demonstration that once the attenuation of the clock signal is controlled, the phase delay can be accurately captured in terms of the first-moment. Furthermore, the form of these metrics and their relationship to one another provides an excellent foundation for various forms of clock tree optimization
  • Keywords
    RC circuits; circuit optimisation; delay estimation; digital integrated circuits; integrated circuit design; linear network analysis; linear network synthesis; poles and zeros; timing circuits; transient response; HF clock signals; IC clock frequencies; RC clock trees; RC transmission lines; RLC clock trees; clock signals distribution; clock tree optimization; clock tree performance optimisation; clock tree skew optimisation; first-moment; fundamental frequency; high-frequency effects; impulse response; inductance effects; phase delay; reflections; signal attenuation; underdamped responses; Attenuation; Circuit synthesis; Clocks; Delay; Design automation; Frequency domain analysis; Frequency measurement; Inductance; Reflection; Signal synthesis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.748159
  • Filename
    748159