Title :
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations
Author :
Naiknaware, Ravindranath ; Fiez, Terri S.
Author_Institution :
Washington State University
fDate :
3/1/1999 12:00:00 AM
Keywords :
CMOS analog integrated circuits, design automation, design methodology, integrated circuit layout; Analog circuits; CMOS analog integrated circuits; CMOS process; Capacitors; Design automation; Design methodology; Integrated circuit layout; Integrated circuit yield; Mirrors; Parasitic capacitance;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1999.748181
