• DocumentCode
    1476856
  • Title

    Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations

  • Author

    Naiknaware, Ravindranath ; Fiez, Terri S.

  • Author_Institution
    Washington State University
  • Volume
    34
  • Issue
    3
  • fYear
    1999
  • fDate
    3/1/1999 12:00:00 AM
  • Firstpage
    304
  • Lastpage
    303
  • Keywords
    CMOS analog integrated circuits, design automation, design methodology, integrated circuit layout; Analog circuits; CMOS analog integrated circuits; CMOS process; Capacitors; Design automation; Design methodology; Integrated circuit layout; Integrated circuit yield; Mirrors; Parasitic capacitance;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1999.748181
  • Filename
    748181
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1476856