A multistage amplifier technique with embedded frequency compensation

Author

Ng, Hiok-Tiaq ; Ziazadeh, Ramsin M. ; Allstot, David J.

Author_Institution

Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA

Volume

34

Issue

3

fYear

1999

fDate

3/1/1999 12:00:00 AM

Firstpage

339

Lastpage

347

Abstract

A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-μm n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V/μs average slew rate with 40 pF load

Keywords

CMOS analogue integrated circuits; circuit stability; compensation; integrated circuit design; linear network synthesis; low-power electronics; network topology; operational amplifiers; poles and zeros; sensitivity analysis; wideband amplifiers; 0.6 micron; 102 dB; 3 V; 40 pF; 47 MHz; 6.9 mW; compensation circuits; embedded frequency compensation; fast slewing; high gain; low-power compensation technique; multistage amplifier technique; operational amplifier topology; power efficiency; resistance-capacitance compensation technique; wide bandwidth; Bandwidth; CMOS process; Circuit stability; Circuit topology; Frequency; Network topology; Operational amplifiers; Prototypes; Temperature; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.748185

Filename

748185