Title :
MDSP-II: a 16-bit DSP with mobile communication accelerator
Author :
Kim, Byoung-Woon ; Yang, Jin-Hyuk ; Hwang, Chan-Soo ; Kwon, Young-Su ; Lee, Keun-Moo ; Kim, In-Hyoung ; Lee, Yong-Hoon ; Kyung, Chong-Min
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fDate :
3/1/1999 12:00:00 AM
Abstract :
This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-μm triple-layer metal CMOS process on a 9.7×9.8 mm2 silicon area and was operated up to 50 MHz clock frequency
Keywords :
CMOS digital integrated circuits; Viterbi decoding; application specific integrated circuits; cellular radio; digital signal processing chips; equalisers; high-speed integrated circuits; telecommunication computing; 0.6 micron; 16 bit; 19 MIPS; 50 MHz; GSM baseband functions; MDSP-II; Viterbi equalization; application-specific hardware block; digital signal processor; instruction set; mobile communication accelerator; programmable fixed-point DSP; triple-layer metal CMOS process; Acceleration; Baseband; CMOS process; Digital signal processing; Digital signal processors; GSM; Hardware; Mobile communication; Silicon; Viterbi algorithm;
Journal_Title :
Solid-State Circuits, IEEE Journal of
