• DocumentCode
    1476939
  • Title

    Reducing switching activity on datapath buses with control-signal gating

  • Author

    Kapadia, Hema ; Benini, Luca ; De Micheli, Giovanni

  • Author_Institution
    Comput. Syst. Lab., Stanford Univ., CA, USA
  • Volume
    34
  • Issue
    3
  • fYear
    1999
  • fDate
    3/1/1999 12:00:00 AM
  • Firstpage
    405
  • Lastpage
    414
  • Abstract
    This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. The “observability don´t-care condition” of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register transfer level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead. It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead
  • Keywords
    VLSI; clocks; integrated circuit design; logic CAD; low-power electronics; microprocessor chips; observability; reduced instruction set computing; control-signal gating; datapath buses; dynamic switching power; gated control signals; integer execution units; minimal overhead; observability don´t-care condition; power dissipation; quiescent state; register transfer level description; switching activity; two-way superscalar RISC microprocessor; Automatic control; Clocks; Delay; Energy management; Logic; Microprocessors; Power dissipation; Power system management; Power system reliability; Signal synthesis;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.748193
  • Filename
    748193